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Very long instruction word
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21	Lecture 7: Vector Processing Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-02-13 14:52:32 Mathematics Abstract algebra Linear algebra Central processing unit Computer architecture Vector processor Superscalar Cray-1 Very long instruction word Algebra Parallel computing Computing
22	Resource-Constrained Software Pipelining Alexandru Nicolau Department of Information and Computer Science University of California, Irvine Irvine, CA 92717 Add to Reading List Source URL: theory.stanford.edu Language: English - Date: 2014-08-19 20:12:12 Compiler optimizations Computer architecture Software pipelining Operations research Scheduling Futures and promises Algorithm Pipeline Very long instruction word Concurrent computing Computing Parallel computing
23	Inter-Block Scoreboard Scheduling in a JIT Compiler for VLIW Processors Technical Report A/392/CRI Benoˆıt Dupont de Dinechin STMicroelectronics STS/CEC Add to Reading List Source URL: www.cri.ensmp.fr Language: English - Date: 2008-06-04 03:10:36 Computing Operations research Instruction scheduling Very long instruction word Scheduling No instruction set computing Block scheduling Schedule List scheduling Education Scheduling algorithms Planning
24	Time-Indexed Formulations and a Large Neighborhood Search for the Resource-Constrained Modulo Scheduling Problem Benoˆıt Dupont de Dinechin STMicroelectronics STS/CEC 12, rue Jules Horowitz - BP 217. FGrenoble b Add to Reading List Source URL: www.cri.ensmp.fr Language: English - Date: 2007-06-06 10:50:57 Operations research Computing Job shop scheduling Mathematical optimization Multiplicative order Scheduling Modulo Very long instruction word Software pipelining Compiler optimizations Modular arithmetic Mathematics
25	Automatic Streamization of Image Processing Applications Pierre Guillou, Fabien Coelho, and François Irigoin MINES ParisTech, PSL Research University Add to Reading List Source URL: www.cri.ensmp.fr Language: English - Date: 2014-09-09 10:48:46 Models of computation Programming paradigms Massively parallel processor array Dataflow architecture Dataflow programming Multi-core processor Dataflow Very long instruction word Directed acyclic graph Computing Parallel computing Computer architecture
26	Lecture 23: Goodbyte to Computer Architecture, Future Predictions, and Your Cal Cultural Heritage Professor David A. Patterson Computer Science 252 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-05-08 14:16:37 Central processing unit Parallel computing Classes of computers Microprocessors Superscalar X86 Very long instruction word Instruction-level parallelism Reduced instruction set computing Computer architecture Computer hardware Computing
27	Partial Evaluation for Scientic Computing: The Supercomputer Toolkit Experience Andrew A. Berlin Xerox Palo Alto Research Center Rajeev J. Surati Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:06:08 Parallel computing Automatic parallelization Very long instruction word Cell Microarchitecture Supercomputer Program optimization 64-bit Central processing unit Computing Concurrent computing Computer programming
28	Why GPUs? Robert Strzodka (MPII), Dominik Göddeke (TUDo), Dominik Behr (AMD) PPAM 2009 – Conference on Parallel Processing and Applied Mathematics Wroclaw, Poland, September 13-16, 2009 Add to Reading List Source URL: gpgpu.org Language: English - Date: 2014-08-11 19:24:48 Computer hardware Instruction-level parallelism Stream processing Central processing unit Speedup GPGPU Very long instruction word Computer memory Computing Parallel computing Computer architecture
29	Scientific Computing on GPUs Coding Demos Add to Reading List Source URL: gpgpu.org Language: English - Date: 2014-08-11 19:25:10 Graphics hardware Video cards Computer architecture Parallel computing OpenCL Nvidia Very long instruction word CUDA Graphics processing unit GPGPU Computer hardware Computing
30	Microsoft PowerPoint - HC18.120.S1T2.Heterogeneous Multiprocessing for Efficient Multi-Standard High Definition Video Decoding. Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:51:44 Videotelephony Digital signal processors Digital signal processing Parallel computing Video compression TriMedia Very long instruction word Media processor NXP Semiconductors Electronic engineering Electronics Computing

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